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| 1 p/n:pm1084 rev. 0.0, mar. 17, 2004 mx28f640c3bt/b 64m-bit [4m x16] cmos single voltage 3v only flash memory advanced information ? automatic suspend enhance - word write suspend to read - sector erase suspend to word write - sector erase suspend to read register report automatic sector erase, full chip erase, word write and sector lock/unlock configuration status reply - detection of program and erase operation comple- tion. - command user interface (cui) - status register (sr) data protection performance - include boot sectors and parameter and main sectors to be block/unblock 100,000 minimum erase/program cycles common flash interface (cfi) 128-bit protection register - 64-bit unique device identifier - 64-bit user-programmable latch-up protected to 100ma from -1v to vcc+1v package type: - 48-pin tsop (12mm x 20mm) features bit organization: 4,194,304 x 16 single power supply operation - 3.0v only operation for read, erase and program operation - vcc=vccq=2.7~3.6v - operating temperature:-40 c~85 c fast access time : 90/120ns low power consumption - 9ma maximum active read current, f=5mhz (cmos input) - 21ma program erase current maximum (vpp=1.65~3.6v) - 7ua typical standby current under power saving mode sector architecture - sector erase (sector structure : 4kword x 2 (boot sectors), 4kword x 6 (parameter sectors), 32kword x 127 (parameter sectors) - top/bottom boot auto erase (chip & sector) and auto program - automatically program and verify data at specified address general description the mx28f640c3bt/b is a 64-mega bit flash memory organized as 4m words of 16 bits. the 1m word of data is arranged in eight 4kword boot and parameter sectors, and 127 32kword main sector which are individually erasable. mxic's flash memories offer the most cost- effective and reliable read/write non-volatile random ac- cess memory. the mx28f640c3bt/b is packaged in 48-pin tsop. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard mx28f640c3bt/b offers access time as fast as 90ns, allowing operation of high-speed micropro- cessors without wait states. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the mx28f640c3bt/b uses a command register to man- age this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom compatibility. mxic flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced
2 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. the mx28f640c3bt/b uses a 2.7v~3.6v vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. the dedicated vpp pin gives complete data protection when vpp< vpplk. a command user interface (cui) serves as the inter- face between the system processor and internal opera- tion of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algo- rithms and timings necessary for erase, full chip erase, word write and sector lock/unlock configuration opera- tions. a sector erase operation erases one of the device's 32k- word sectors typically within 1.0s, 4k-word sectors typi- cally within 0.5s independent of other sectors. each sec- tor can be independently erased minimum 100,000 times. sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector. writing memory data is performed in word increments of the device's 32k-word sectors typically within 0.8s and 4k-word sectors typically within 0.1s. word program sus- pend mode enables the system to read data or execute code from any other memory array location. mx28f640c3bt/b features with individual sectors lock- ing by using a combination of bits thirty-nine sector lock- bits and wp#, to lock and unlock sectors. the status register indicates when the wsm's sector erase, full chip erase, word program or lock configura- tion operation is done. the access time is 90/120ns (telqv) over the operat- ing temperature range (-40 c to +80 c) and vcc supply voltage range of 2.7v~3.6v. mx28f640c3bt/b's power saving mode feature sub- stantially reduces active current when the device is in static mode (addresses not switching). in this mode, the typical iccs current is 7ua (cmos) at 3.0v vcc. as ce# and reset# are at vcc, icc cmos standby mode is enabled. when reset# is at gnd, the reset mode is enabled which minimize power consumption and provide data write protection. a reset time (tphqv) is required from reset# switch- ing high until outputs are valid. similarly, the device has a wake time (tphel) from reset#-high until writes to the cui are recognized. with reset# at gnd, the wsm is reset and the status register is cleared. 3 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 block diagram output buffer output multiplexer data register q0~q7 identifier register command user interface input buffer status register data comparator y-gating 32k-word main sector x127 ....... ....... boot sector 0 boot sector 1 parameter sector 0 parameter sector 1 parameter sector 2 parameter sector 3 parameter sector 4 parameter sector 5 main sector 0 main sector 1 main sector 125 main sector 126 write state machine program/erase voltage switch y decoder input buffer a0~a21 address latch address counter x decoder i/o logic vcc ce# we# oe# reset# wp# vpp vcc gnd 4 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 pin configurations 48 tsop (standard type) (12mm x 20mm) a15 a14 a13 a12 a11 a10 a9 a8 a21 a20 we# reset# vpp wp# a19 a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 vccq gnd q15 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx28f640c3t/b table 1. pin description symbol type description and function a0-a21 input address inputs for memory address. data pin float to high-impedance when the chip is deselected or outputs are disable. addresses are internally latched during a write or erase cycle. q0-q15 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched. outputs array and configuration data. the data pin float to tri-state when the chip is de-selected. ce# input activ ates the device's control logic, input buffers, and sense amplifiers. ce# high de-se- lects the memory device and reduce power consumption to standby level. ce# is active low. reset# input reset deep power down: when reset#=vil, the device is in reset/deep power down mode, which drives the outputs to high z, resets the wsm and minimizes current level. when reset#=vih, the device is normal operation. when reset# transition the device defaults to the read array mode. we# input wr ite enable: to control write to cui and array sector. wr#=vil becomes active. the data and address is latched we# on the rising edge of the second we# pulse. vpp input/supply program/erase power supply:(1.65v~3.6v or 11.4v~12.6v) lower vpp 6 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 sector sector size address range (h) main sector 71 32k word 1b8000-1bffff main sector 72 32k word 1b0000-1b7fff main sector 73 32k word 1a8000-1affff main sector 74 32k word 1a0000-1a7fff main sector 75 32k word 198000-19ffff main sector 76 32k word 190000-197fff main sector 77 32k word 188000-18ffff main sector 78 32k word 180000-187fff main sector 79 32k word 178000-17ffff main sector 80 32k word 170000-177fff main sector 81 32k word 168000-16ffff main sector 82 32k word 160000-167fff main sector 83 32k word 158000-15ffff main sector 84 32k word 150000-157fff main sector 85 32k word 148000-14ffff main sector 86 32k word 140000-147fff main sector 87 32k word 138000-13ffff main sector 88 32k word 130000-137fff main sector 89 32k word 128000-12ffff main sector 90 32k word 120000-127fff main sector 91 32k word 118000-11ffff main sector 92 32k word 110000-117fff main sector 93 32k word 108000-10ffff main sector 94 32k word 100000-107fff main sector 95 32k word 0f0000-0fffff main sector 96 32k word 0f0000-0f7fff main sector 97 32k word 0e8000-0effff main sector 98 32k word 0e0000-0e7fff main sector 99 32k word 0d8000-0dffff main sector 100 32k word 0d0000-0d7fff main sector 101 32k word 0c8000-0cffff main sector 102 32k word 0c0000-0c7fff main sector 103 32k word 0b8000-0bffff main sector 104 32k word 0b0000-0b7fff main sector 105 32k word 0a8000-0affff main sector 106 32k word 0a0000-0a7fff main sector 107 32k word 098000-09ffff main sector 108 32k word 090000-097fff main sector 109 32k word 088000-08ffff main sector 110 32k word 080000-087fff sector sector size address range (h) main sector 111 32k word 078000-07ffff main sector 112 32k word 070000-077fff main sector 113 32k word 068000-06ffff main sector 114 32k word 060000-067fff main sector 115 32k word 058000-05ffff main sector 116 32k word 050000-057fff main sector 117 32k word 048000-04ffff main sector 118 32k word 040000-047fff main sector 119 32k word 038000-03ffff main sector 120 32k word 030000-037fff main sector 121 32k word 028000-02ffff main sector 122 32k word 020000-027fff main sector 123 32k word 018000-01ffff main sector 124 32k word 010000-017fff main sector 125 32k word 008000-00ffff main sector 126 32k word 000000-007fff 7 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 sector structure (bottom) sector sector size address range (h) boot sector 0 4k word 000000-000fff boot sector 1 4k word 001000-001fff parameter sector 0 4k word 002000-002fff parameter sector 1 4k word 003000-003fff parameter sector 2 4k word 004000-004fff parameter sector 3 4k word 005000-005fff parameter sector 4 4k word 006000-006fff parameter sector 5 4k word 007000-007fff main sector 0 32k word 008000-00ffff main sector 1 32k word 010000-017fff main sector 2 32k word 018000-01ffff main sector 3 32k word 020000-027fff main sector 4 32k word 028000-02ffff main sector 5 32k word 030000-037fff main sector 6 32k word 038000-03ffff main sector 7 32k word 040000-047fff main sector 8 32k word 048000-04ffff main sector 9 32k word 050000-057fff main sector 10 32k word 058000-05ffff main sector 11 32k word 060000-067fff main sector 12 32k word 068000-06ffff main sector 13 32k word 070000-077fff main sector 14 32k word 078000-07ffff main sector 15 32k word 080000-087fff main sector 16 32k word 088000-08ffff main sector 17 32k word 090000-097fff main sector 18 32k word 098000-09ffff main sector 19 32k word 0a0000-0a7fff main sector 20 32k word 0a8000-0affff main sector 21 32k word 0b0000-0b7fff main sector 22 32k word 0b8000-0bffff main sector 23 32k word 0c0000-0c7fff main sector 24 32k word 0c8000-0cffff main sector 25 32k word 0d0000-0d7fff main sector 26 32k word 0d8000-0dffff main sector 27 32k word 0e0000-0e7fff main sector 28 32k word 0e8000-0effff main sector 29 32k word 0f0000-0f7fff main sector 30 32k word 0f8000-0fffff sector sector size address range (h) main sector 31 32k word 100000-107fff main sector 32 32k word 108000-10ffff main sector 33 32k word 110000-117fff main sector 34 32k word 118000-11ffff main sector 35 32k word 120000-127fff main sector 36 32k word 128000-12ffff main sector 37 32k word 130000-137fff main sector 38 32k word 138000-13ffff main sector 39 32k word 140000-147fff main sector 40 32k word 148000-14ffff main sector 41 32k word 150000-157fff main sector 42 32k word 158000-15ffff main sector 43 32k word 160000-167fff main sector 44 32k word 168000-16ffff main sector 45 32k word 170000-177fff main sector 46 32k word 178000-17ffff main sector 47 32k word 180000-187fff main sector 48 32k word 188000-18ffff main sector 49 32k word 190000-197fff main sector 50 32k word 198000-19ffff main sector 51 32k word 1a0000-1a7fff main sector 52 32k word 1a8000-1affff main sector 53 32k word 1b0000-1b7fff main sector 54 32k word 1b8000-1bffff main sector 55 32k word 1c0000-1c7fff main sector 56 32k word 1c8000-1 cffff main sector 57 32k word 1d0000-1d7fff main sector 58 32k word 1d8000-1 dffff main sector 59 32k word 1e0000-1e7fff main sector 60 32k word 1e8000-1effff main sector 61 32k word 1f0000-1f7fff main sector 62 32k word 1f8000-1fffff main sector 63 32k word 200000-207fff main sector 64 32k word 208000-20ffff main sector 65 32k word 210000-217fff main sector 66 32k word 218000-21ffff main sector 67 32k word 220000-227fff main sector 68 32k word 228000-22ffff main sector 69 32k word 230000-237fff main sector 70 32k word 238000-23ffff 8 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 sector sector size address range (h) main sector 71 32k word 240000-247fff main sector 72 32k word 248000-24ffff main sector 73 32k word 250000-257fff main sector 74 32k word 258000-25ffff main sector 75 32k word 260000-267fff main sector 76 32k word 268000-26ffff main sector 77 32k word 270000-277fff main sector 78 32k word 278000-27ffff main sector 79 32k word 280000-287fff main sector 80 32k word 288000-28ffff main sector 81 32k word 290000-297fff main sector 82 32k word 298000-29ffff main sector 83 32k word 2a0000-2a7fff main sector 84 32k word 2a8000-2affff main sector 85 32k word 2b0000-2b7fff main sector 86 32k word 2b8000-2bffff main sector 87 32k word 2c0000-2c7fff main sector 88 32k word 2c8000-2cffff main sector 89 32k word 2d0000-2d7fff main sector 90 32k word 2d8000-2dffff main sector 91 32k word 2e0000-2e7fff main sector 92 32k word 2e8000-2effff main sector 93 32k word 2f0000-2f7fff main sector 94 32k word 2f8000-2fffff main sector 95 32k word 300000-307fff main sector 96 32k word 308000-30ffff main sector 97 32k word 310000-317fff main sector 98 32k word 318000-31ffff main sector 99 32k word 320000-327fff main sector 100 32k word 328000-32ffff main sector 101 32k word 330000-337fff main sector 102 32k word 338000-33ffff main sector 103 32k word 340000-347fff main sector 104 32k word 348000-34ffff main sector 105 32k word 350000-357fff main sector 106 32k word 358000-35ffff main sector 107 32k word 360000-367fff main sector 108 32k word 368000-36ffff main sector 109 32k word 370000-377fff main sector 110 32k word 378000-37ffff sector sector size address range (h) main sector 111 32k word 380000-387fff main sector 112 32k word 388000-38ffff main sector 113 32k word 390000-397fff main sector 114 32k word 398000-39ffff main sector 115 32k word 3a0000-3a7fff main sector 116 32k word 3a8000-3affff main sector 117 32k word 3b0000-3b7fff main sector 118 32k word 3b8000-3bffff main sector 119 32k word 3c0000-3c7fff main sector 120 32k word 3c8000- 3cffff main sector 121 32k word 3d0000-3d7fff main sector 122 32k word 3d8000- 3dffff main sector 123 32k word 3e0000-3e7fff main sector 124 32k word 3e8000-3effff main sector 125 32k word 3f0000-3f7fff main sector 126 32k word 3f8 000-3fffff 9 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 2 principles of operation the product includes an on-chip wsm to manage sec- tor erase, word write and lock-bit configuration functions. after initial device power-up or return from reset mode (see section on bus operations), the device defaults to read array mode. manipulation of external memory con- trol pins allow array read, standby and output disable operations. status register and identifier codes can be accessed through the cui independent of the vpp voltage. all functions associated with altering memory contents-sec- tor erase, word write, sector lock/unlock, status and iden- tifier codes - are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the sector erase, word write and sector lock/unlock. the internal algorithms are regulated by the wsm, including pulse repetition, internal verifica- tion and margining of data. addresses and data are in- ternally latched during write cycles. address is latched at falling edge of ce# and data latched at rising edge of we#. writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. interface software that initiates and polls progress of sector erase, full chip erase, word write and sector lock/ unlock can be stored in any sector. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. sector erase sus- pend allows system software to suspend a sector erase to read/write data from/to sectors other than that which is suspend. word write suspend allows system software to suspend a word write to read data from any other flash memory array location. with the mechanism of sector lock, memory contents cannot be altered due to noise or unwanted operation. when reset#=vih and vcc 11 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 4 command definitions when the vpp voltage < vpplk, read operations from the status register, identifier codes, or sectors are en- abled. placing vpp on vpph1/2 enables successful sector erase, full chip erase, word write and sector lock/ unlock. device operations are selected by writing specific com- mands into the cui. table 3 defines these commands. table 2. bus operation 1,2 mode notes reset ce# oe# we# q0~q15 read 1,2 vih vil vil vih dout output disable 2 vih vil vih vih high z standby 2 vih vih x x high z reset 2 vil x x x high z write 2,3,4,5 vih vil vih vil din notes: 1. refer to dc characteristics for vpplk, vpp1, vpp2, vpp3 voltage. 2. x can be vil or vih for pin and addresses. 3. reset# at gnd 0.2 to ensure the lowest power consumption. 4. refer to table 3 for valid din during a write operation. 5. to program or erase the lockable sectors holds wp# at vih. 12 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 table 3. command definition (1) command bus notes first bus cycle second bus cycle cycles operation address data operation address data required (1) (2) (3) (1) (2) (3) read array 1 write x ffh read configuration > 2 3,4 write x 90h read ia id read query 2 2,7 write x 98h read qa qd read status register 2 3 write x 70h read x srd clear status register 1 3 write x 50h sector erase/confirm 2 write x 20h write ba d0h word write 2 5 write x 40h/10h write wa wd program/erase suspend 1 write x b0h program/erase resume 1 write x d0h sector lock 2 write x 60h write ba 01h sector unlock 2 6 write x 60h write ba d0h lock-down sector 2 write x 60h write ba 2fh protection program 2 write x c0h write pa pph notes: 1. bus operation are defined in table 2 and referred to ac timing waveform. 2. x=any address within device ia=id-code address (refer to table 4) ba=sector within the sector being erased wa=address of memory location to be written qa=query address, qd=query data 3. data is latched from the rising edge of we# or ce# (whichever goes high first) srd=data read from status register, see table 6 for description of the status register bits. wd=data to be written at location wa. id=data read from identifier codes 4. following the read configuration codes command, read operation access manufacturer, device codes, sector lock/unlock codes, see chapter 4.2. 5. either 40h or 10h are recognized by the wsm as word write setup. 6. the sector unlock operation simultaneously clear all sector lock. 7. read query command is read for cfi query information. 13 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 4.1 read array command upon initial device power-up and after exit from reset mode, the device defaults to read array mode. this op- eration is also initiated by writing the read array com- mand. the device remains enabled for reads until an- other command is written. once the internal wsm has started a sector erase, word write or sector lock con- figuration the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via a sector erase suspend or word write suspend command. if reset#=vil device is in read read array command mode, this read opera- tion no longer requires vpp. the read array command functions independently of the vpp voltage and reset# can be vih. 4.2 read configuration codes command the configuration code operation is initiated by writing the read configuration codes command (90h). to re- turn to read array mode, write the read array command (ffh). following the command write, read cycles from addresses shown in table 4 retrieve the manufacturer, device, sector lock configuration codes (see table 4 for configuration code values). to terminate the operation, write another valid command. like the read array com- mand, the read configuration codes command func- tions independently of the vpp voltage and reset# can be vih. following the read configuration codes com- mand, the information is shown: code address data (a19-a0) (q15-q0) manufacturer code 00000h 00c2h device code 00001h 88cc/88cdh sector lock configuration xx002h lock - sector is unlocked q0=0 - sector is locked q0=1 - sector is locked-down q1=1 protection register lock 80 pr-lk protection register 81-88 pr table 4: id code 4.3 read status register command cui writes read status command (70h). the status reg- ister may be read to determine when a sector erase, word write or lock-bit configuration is complete and whether the operation completed successfully. (refer to table 6) it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the sta- tus register until another valid command is written. the status register contents are latched on the falling edge of ce# or oe#, whichever occurs. ce# or oe# must toggle to vih before further reads to update the status register latch. the read status register command func- tions independently of the vpp voltage. reset# can be vih. 4.4 clear status register command status register bits sr.5, sr.4, sr.3 or sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command (50h). these bits indicate various failure conditions (see table 6). by allowing sys- tem software to reset these bits, several operations (such as cumulatively erasing multiple sectors or writing sev- eral words in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written on cui. it functions indepen- dently of the applied vpp voltage. reset# can be vih. this command is not functional during sector erase or word write suspend modes. 14 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 4.5 sector erase command erase is executed one sector at a time and initiated by a two-cycle command. a sector erase setup is first writ- ten (20h), followed by a sector erase confirm (d0h). this command sequence requires appropriate sequencing and an address within the sector to be erased. sector pre- conditioning, erase, and verify are handled internally by the wsm. after the two-cycle sector erase sequence is written, the device automatically outputs status register data when read (see figure 8). the cpu can detect sec- tor erase completion by analyzing the output data of the status register bit sr.7. when the sector erase is complete, status register bit sr.5 should be checked. if a sector erase error is de- tected, the status register should be cleared before sys- tem software attempts corrective actions. the cui re- mains in read status register mode until a new com- mand is issued. this two-step command sequence of set-up followed by execution ensures that sector contents are not acciden- tally erased. an invalid sector erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable sector erasure can only occur when 2.7v~3.6v and vpp=vpph1/2. in the ab- sence of this high voltage, sector contents are protected against erasure. if sector erase is attempted while vpp 16 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 4.9 sector lock/unlock /lock-down command 4.9.1 sector locked state the default status of all sectors when power-up or reset is locked. any attempt on program or erase operations will result in an error on bit sr.1 of a locked sector. the status of a locked sector can be changed to unlocked or lock-down using software commands. an unlocked sec- tor can be locked by writing the sector lock command sequence, 60h followed by 01h. 4.9.2 sector unlocked state an unlocked sector can be programmed or erased. all unlocked sector return to the locked state when the de- vice is either reset or powered down. the status of an unlocked sector can be changed to locked or locked- down using software commands. a locked sector can be unlocked by writing unlock command sequence, 60h followed by d0h. 4.9.3 sector locked-down state sectors which are locked-down are protected from pro- gram and erase operation; however, the protection sta- tus of three sectors cannot be changed using software commands alone. any sector locked or unlocked can be locked-down by writing the lock-down command se- quence, 60h followed by 2fh. when the device is reset or powered down, the locked-down sectors will revert to the locked state. the status of wp# will determine the function of sector lock-down and is summarized is followed: wp# sector lock-down description wp#=0 - sectors are protected from program, erase, and lock status changes wp#=1 - the sector lock-down function is disabled - an individual lock-down sector can be un locked and relocked via software command. once wp# goes low, sectors that previously locked-down returns to lock-down state regardless of any changes when wp# was high. 4.9.4 read sector lock status the lock status of every sector can be read through read configuration mode. to enter this mode first com- mand write 90h to the device. the next sector reads at address +00002 will output the lock status of this sec- tor. the lock status can be read from the lowest two output pins q0 and q1. q0, q0 indicates the sector lock/ unlock status and set by the lock command and cleared by the unlock command. when entering lock-down, the lock status is automatically set. q1 indicates lock-down status and is set by the lock-down command. it cannot be further cleared by software, only by device reset or power-down. sector lock configuration table lock status data sector is unlocked q0=0 sector is locked q0=1 sector is locked-down q1=1 in addition, sector lock-down is cleared only when the device is reset or powered down. 17 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 4.9.5 sector locking while erase suspend the sector lock status can be performed during an erase suspend by using standard locking command sequences to unlock, lock, or lock-down a sector. in order to change sector locking during an erase opera- tion, the write erase suspend command (b0h) is placed first; then check the status register until it is shown that the actual erase operation has been suspended. subse- quent writing the desired lock command sequence to a sector and the lock status will be changed. when com- pleting any desired lock, read or program operation, re- sume the erase operation with the erase resume com- mand (d0h). if a sector is locked or locked-down during the same 4.9.6 status register error checking the operation of locking system for this device can be used the term "state (x,y,z)" to specify locking status, where x=value of wp#, y=bit q1 of the sector lock sta- tus register, and z=bit q0 of the sector lock status regis- ter. q0 indicates if a sector is locked (1) or unlocked (0). q1 indicates if a sector has been locked-down(1) or not (0). current state erase/prog. lock command input result (next state) (x, y, z)= operation if (x, y, z)= wp# q1 q0 name enable ? lock unlock lock-down 0 0 0 unlocked yes (001) u nchanged (011) 0 0 1 locked (default) no u nchanged (000) (011) 0 1 1 locked-down no unchanged unchanged unchanged 1 0 0 unlocked yes (101) u nchanged (111) 1 0 1 locked no u nchanged (100) (111) 1 1 0 lock-down disabled yes (111) u nchanged (111) 1 1 1 lock-down disabled no u nchanged (110) unc hanged table 5. sector locking state transitions sector is being placed in erase suspend, the locking sta- tus bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operation cannot be performed during a program suspend. 18 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 table 6. status register definition sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = sector erase suspend status (ess) 1 = sector erase suspended 0 = sector erase in progress/completed sr.5 = erase status (es) 1 = error in programming 0 = successful sector erase or clear sector lock- bits sr.4 = program status (ps) 1 = error in programming 0 = successful programming sr.3 = vpp status (vpps) 1 = vpp low detect, operation abort 0 = vpp ok sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed sr.1 = sector lock status 1 =program/erase attempted an a locked sector; operation aborted 0 = no operation to locked sectors sr.0 = reserved for future enhancements (r) notes: check wsm bit first to determine word program or sec- tor erase completion, before checking program or erase status bits. when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to "1". ess bit re- mains set to "1" until an erase resume command is issued. when this bit (sr.5) is set to "1", it means wsm is unable to verify successful sector erasure. when this bit is set to "1", wsm has attempted but failed to program a word. sr.3 bit is not guaranteed to report accurate feedback between vpplk and vpp min. when program suspend is issued, wsm halts the ex- ecution and sets both wsms and sr.2 bit to "1". sr.2 remains set to "1" until a program resume command is issued. if a program or erase operation is attempted to one of the locked sectors, this bit is set by the wsm. the op- eration specified is aborted and the device is returned to read status mode. sr. 0 is reserved for future use and should be masked out when polling the status register. wsms bess es ps vpps pss bls r 76543 2 1 0 19 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 5. 128-bit protection register the 128-bits of protection register are divided into two 64-bit segments. one of the segments is programmed at mxic side with unique 64-bit number; where changes are forbidden. the other segment is left empty for cus- tomer to program. once the customer segment is pro- grammed, it can be locked to prevent further reprogram- ming. 5.1 protection register read & programming the protection register is read in the configuration read mode, which follows the stated command bus defini- tions. the device is switched to this read mode by writing the read configuration command (90h). once this mode, read cycles from addresses shown in table 7 will re- trieve the specified information. to return to read array mode, write the read array command (ffh). two-cycle protection program command is used to pro- gram protection register bits. the 64-bit register is pro- grammed 16-bits at a time. first write c0h protection program setup. the next write to the device will latch in address and data and program the specified location. the allowable address are also show in table 7. refer to figure 6 for the protection register programming flow- chart. any attempt to address protection program command onto undefined protection register address space will result in a status register error (sr.4 set to "1"). in addition, attempting to program or to previously locked protection register segment will result in a status regis- ter error (sr.4=1, sr.1=1). word user a7 a6 a5 a4 a3 a2 a1 a0 lock both 1 0 0 0 0 0 0 0 0 factory 1 0 0 0 0 0 0 1 1 factory 1 0 0 0 0 0 1 0 2 factory 1 0 0 0 0 0 1 1 3 factory 1 0 0 0 0 1 0 0 4 customer 1 0 0 0 0 1 0 1 5 customer 1 0 0 0 0 1 1 0 6 customer 1 0 0 0 0 1 1 1 7 customer 1 0 0 0 1 0 0 0 table 7. word-wide protection register addressing 5.2 protection register locking the user-programmable segment of the protection reg- ister is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at mxic to protect the unique device number. this bit is set using the unique device number. this bit is set using the protection program command to program "fffd" to pr-lock location. after these bits have been pro- grammed, no further changes can be made to the value stored in the protection register. protection program com- mand to a locked section will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1). protection register lockout state is not reversible. protection register purpose bit address 88h~85h 4 word user program register 84h~81h 4 word factory program register 80h(bit0 & bit1) protection register lock (pr-lock) table 8. protection register memory map notes: 1. set address bit a21-a15=1 for top boot device. 2. set address bit a21-a15=0 for bottom boot device. 3. the address not specified in above are don't care. 20 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 6 electrical specifications 6.1 absolute maximum ratings operating temperature during read, sector erase, word write . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c storage temperature . . . . . . . . . . . . . .-65 o c to +125 o c voltage on any pin (except vcc and vpp with respect to gnd) . . . . . . . . . . .-0.5 v to +5v (1) vcc supply voltage . . . . . . . . . . . . .-0.2v to +4.6v (2) vpp supply voltage (for sector erase and vpp with respect to gnd) . . . . . . . .-0.5v to +4.6v (1,2) vcc and vccq supply voltage with respect to gnd. . . . . . . . . . . . . . . . .-0.2v to +3.6v (1) output short circuit voltage . . . . . . . . . . . . .100ma warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and ex- tended exposure beyond the "operation conditions" may affect device reliability. 6.2.1 capacitance (1) (ta=+25 o c, f=1mhz) symbol parameter min. max. unit notes ta operating temperature -40 +85 o c vcc1 vcc supply voltage 2.7 3.6 v 1 vccq1 i/o supply voltage 2.7 3.6 v 1 vpp1 supply voltage 1.65 3.6 v 1 vpp2 supply voltage 11.4 12.6 v 1 cycling sector erase cycling 100,000 2 6.2 operating conditions (temperature and vcc operating conditions) symbol parameter typ. max. unit t est condition cin input capacitance 6 8 pf vin=0.0v cout output capacitance 10 12 pf vout=0.0v note: 1. sampled, not 100% tested. 1. minimum dc voltage is -0.5v on input pins. during transitions, this level may undershoot to -2.0v for pe- riods <20ns. maximum dc voltage on input/output pins to vcc+0.5v which during transition; may overshoot to vcc+2.0v for periods <20ns. 2. output shorted for no more than one second. no more than one output shorted at a time. note: 1. vcc and vccq must share the same supply when they are in the vcc1 range. 2. applying vpp=11.4~12.6v during a program/erase can only be done for a maximum of 1000 cycles on the main sectors and 2500 cycles on the parameter sectors. vpp may be connected to 12v for a total of 80 hours maximum. 21 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 6.2.2 ac input/output test conditions figure 1. transient input/output reference waveform test points vccq/2 output note:ac test inputs are driven at vccq/2 for a logic "1" and 0.0v for a logic "0". vccq 0.0 input vccq/2 figure 2. switching test circuits test specifications test condition 90 120 unit output load 1 ttl gate output load capacitance, cl 30 100 pf (including jig capacitance) input rise and fall times 5 ns input pulse levels 0.0-3.0 v input timing measurement 1.5 v reference levels output timing measurement 1.5 v reference levels device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm 3.3v 22 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 6.2.3 ac characteristic -- read only operation (1) -90 -110 sym. parameter notes min. max. min. max. unit tavav read cycle time 90 110 ns tavqv address to output delay 90 110 ns telqv ce# to output delay 2 90 110 ns tglqv oe# to output delay 2 30 30 ns tphqv reset# to output delay 150 150 ns telqx ce# to output in low z 3 0 0 ns tglqx oe# to output in low z 3 0 0 ns tehqz ce# to output in high z 3 20 20 ns tghqz oe# to output in high z 3 20 20 ns toh output hold from address, 3 0 0 ns ce#, or oe# change, whichever occurs first notes: 1. see ac waveform: read operations. 2. oe# may be delayed up to telqv-tglqv after the falling edge of ce# without impact on telqv. 3. sampled, but not 100% tested. 4. see test configuration. 23 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 figure 3. read-only operation ac waveform tehqz tavav tghqz tglqv telqv telqx tavqv tphqv tglqx toh high z high z valid output address stable device and address selection data valid standby vih vil addresses(a) vih vil ce# (e) vih vil oe# (g) vih vil we# (w) vih vil reset# (p) voh vol data (q) 24 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 6.2.5 ac characteristic -- write operation notes: 1. write timing characteristics during erase suspend are the same as during write-only operations. 2. refer to table 5 for valid ain or din. 3. sampled, not 100% tested. 4. write pulse width (twp) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, twp=twlwh=teleh=telwh. similarly, write pulse width high (twph) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low first). hence, twph=twhwl=tehel=tehwl. 5. see test configuration. 6. vcc max = 3.3v. -90 -110 sym. parameter note min. min. unit tphwl/tphel reset# high recovery to we#(ce#) going low 150 150 ns telwl/twlel ce#(we#) setup to we#(ce#) going low 0 0 ns teleh/twlwh we#(ce#) pulse width 4 50 70 ns tdvwh/tdveh data setup to we#(ce#) going high 2 50 60 ns tavwh/taveh address setup to we#(ce#) going high 2 50 70 ns twheh/tehwh ce#(we#) hold time from we#(ce#) high 0 0 ns twhdx/tehdx data hold time from we#(ce#) high 2 0 0 ns twhax/tehax address hold time from we#(ce#) high 2 0 0 ns twhwl/tehel we#(ce#) pulse width high 4 30 30 ns tvpwh/tvpeh vpp setup to we#(ce#) going high 3 200 200 ns tqvvl vpp hold from valid srd 3 0 0 ns tbhwh/tbheh wp# setup to we#(ce#) going high 3 0 0 ns tqvbl wp# hold from valid srd 3 0 0 ns twhgl we# high to oe# going low 3 30 30 ns 25 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 figure 4. program and erase operation ac waveform notes: 1. ce# must be toggled low when reading status register data. we# must be inactive (high) when reading status register data. a. vcc power-up and standby. b. write program or erase setup command. c. write valid address and data (for program) or erase confirm command. d. automated program or erase delay. e. read status register data (srd): reflects completed program/erase operation. f. write read array command. tvpwh (tvpeh) tqvvl twhwl (tehel) twhgl tphwl (tphel) (note 1) (note 1) teleh (twlwh) twhdx (tehdx) twheh (tehwh) telwl (twlel) tavwh (taveh) twhax (tehax) tdvwh (teveh) tbhwh (tbheh) tqvbl high z din address (a) ab cd e f vih vil oe#(g) vih vil vih vil ce(we#)[e(w)] vih disable enable vil we#,(ce#)[w(e)] vih vil data[q] voh vol reset#[p] vih vil vpph1 vpph2 vpplk vil wp# vpp[v] din ain ain din valid srd 26 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 6.2.5 erase and program timing (1) vpp 1.65v-3.6v 11.4v-12.6v symbol parameter note typ(1) max typ(1) max unit tbwpb 4-kw parameter sector 2,3 0.10 0.30 0.03 0.12 s word program time(word) tbwmb 32-kw main sector 2,3 0.8 2.4 0.24 1 s word program time twhqv1/ word program time 2,3 12 200 8 185 us tehqv1 twhqv2/ 4-kw parameter sector 2,3 0.5 4 0.4 4.0 s tehqv2 erase time twhqv3/ 32-kw main sector 2,3 1 5 0.6 5 s tehqv3 erase time twhrh1/ program suspend latency 3 5 16 15 20 us tehrh1 twhrh2/ erase suspend latency 3 5 20 15 20 us tehrh2 notes: 1. typical values measured at ta=+25 c and nominal voltage. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. 27 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 ac characteristic -- under reset operation sym. parameter vcc=2.7v~3.6v unit notes min. max. tplph reset# low to reset during read 100 ns 2,4 (if reset# is tied to vcc, this specification is applicable) tplrh1 reset# low to reset during sector erase 22 us 3,4 tplrh2 reset# low to reset during program 12 us 3,4 notes: 1. see section 3.4 for a full description of these conditions. 2. if tplph is < 100ns the device may still reset but this is not guaranteed. 3. if reset# is asserted while a sector erase or word program operation is not executing, the reset will complete within 100ns. 4. sampled, but not 100% tested. figure 5. reset# waveform tplph tplrh abort complete tphqv tphwl tphel tphqv tphwl tphel vih vil (a) reset during read mode tplph vih vil (b) reset during program or sector erase, tplph < tplrh tplrh abort complete deep power- down tphqv tphwl tphel tplph vih vil reset# (p) (c) reset program or sector erase, tplph > tplrh reset# (p) reset# (p) 28 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 6.2.6 dc characteristics vcc 2.7v-3.6v sym. parameter note typ. max. unit t est conditions ili input load current 1,2 1 ua vcc=vcc max., vccq=vccq max. vin=vccq or gnd ilo output leakage 1,2 0.2 10 ua vcc=vcc max., vccq=vccq max. current vin=vccq or gnd iccs vcc standby current 1 7 15 ua vcc=vcc max., ce#=reset#=vccq or during program/erase suspend wp#=vccq or gnd iccd vcc power-down current 1,2 7 15 ua vcc=vcc max., vccq=vccq max. vin=vccq or gnd,reset#=gnd 0.2v iccr vcc read current 1,2,3 9 18 ma vcc=vcc max.,vccq=vccq max. oe#=vih, ce#=vil f=5mhz, iout=0ma, inputs=vil or vih ippd vpp deep power- 1 0.2 5 ua reset#=gnd 0.2v down current vpp < vcc iccw vcc program current 1,4 18 55 ma vpp=vpp1, program in progress icce vcc erase current 1,4 16 45 ma vpp=vpp1, erase in progress icces vcc erase suspend 1,4 7 15 ma ce#=vcc, current erase suspend in progress ippr vpp read current 1,4 2 15 ua vpp < vcc ippw vpp program current 1,4 0.05 0.1 ma vpp=vpp1, program in progress ippe vpp erase current 1,4 0.05 0.1 ma vpp=vpp1, program in progress vil input low voltage -0.4 vcc* v 0.22v vih input high voltage 2.0 vccq v +0.3v vol output low voltage -0.1 0.1 v vcc=vcc min, vcc=vccq min iol=100ua voh output high voltage vccq v vcc=vcc min, vcc=vccq min -0.1v ioh=-100ua vpplk vpp lock-out voltage 6 1.0 v co mplete write protection vpp1 vpp during program/ 6 1.65 3.6 v vpp2 erase operations 6,7 11.4 12.6 v vlko vcc prog/erase lock voltage 1.5 v vlko2 vccq prog/erase 1.2 v lock voltage 29 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 notes: 1. all currents are in rms unless otherwise noted. typical values at nominal vcc, ta=+25 c. 2. the test conditions vcc max, vccq max, vcc min, and vccq min refer to the maximum or minimum vcc or vccq voltage listed at the top of each column. vcc max=3.3v for 0.25um 32-mbit devices. 3. power savings (mode) reduces iccr to approximately standby levels in static operation (cmos inputs). 4. sampled, but not 100% tested. 5. icces and iccws are specified with device de-selected. if device is read while in erase suspend, current draw is sum of icces and iccr. if the device is read while in program suspend, current draw is the sum of iccws and iccr. 6. erase and program are inhibited when vpp 31 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 figure 7. program suspend/resume flowchart bus command comments operation write program data=b0h suspend addr=x write read status data=70h addr=x read status register data toggle ce# or oe# to update status register data addr=x standby check sr.7 1=wsm ready 0=wsm busy stanby check sr.2 1=program suspended 0=program completed write read array data=ffh addr=x read read array data from sector other than the one being programmed. write program data=d0h resume addr=x start program write resumed program completed write b0h write 70h read status register 0 0 1 write ffh read array data write d0h sr.7= 1 sr.2= ye s no done reading read array data write ffh 32 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 figure 8. automated sector erase flowchart bus command comments operation write erase setup data=20h addr=within sector to be erased write erase data=d0h confirm addr=within sector to be erased read status register data toggle ce# or oe# to update status register data standby check sr.7 1=wsm ready 0=wsm busy repeat for subsequent block erasures. full status check can be done after each sector erase or after a sequence of sector erasures. write ffh after the last write operation to reset device to read array mode. bus command comments operation standby check sr.3 1=vpp low detect standby check sr.4, 5 both 1=command sequence error standby check sr.5 1=sector erase error standby check sr.1 1=attempted erase of locked sector- erase aborted sr.1 and sr.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1,3,4,5 are only cleared by the clear status reg- ister command, in cases where multiple sectors are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. start write 20h write d0h and block address full status check if desired sector erase complete read status register suspend erase loop 0 no ye s 1 sr.7= suspend erase read status register data(see above) full status check procedure sector erase successful sr.3= 0 0 0 0 vpp range error 1 command sequence error 1 sector erase error 1 sr.4,5= sr.5= attempted erase of locked sector - aborted 1 sr.1= 33 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 figure 9. erase suspend/resume flowchart bus command comments operation write erase data=b0h suspend addr=x write read status data=70h addr=x read status register data toggle ce# or oe# to update status register data addr=x standby check sr.7 1=wsm ready 0=wsm busy stanby check sr.6 1=erase suspended 0=erase completed write read array data=ffh addr=x read read array data from sector other than the one being erased. write erase data=d0h resume addr=x start erase write resumed erase completed write b0h write 70h read status register 0 0 1 write ffh read array data write d0h sr.7= 1 sr.6= ye s no done reading read array data write ffh 34 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 figure 10. locking operations flowchart bus command comments operation write config. setup data=60h addr=x write lock, unlock data=01h (sector lock) or lockdown d0h(sector unlock) 2fh(sector lockdown) addr=within sector to lock write read data=90h (optional) configuration addr=x read sector lock sector lock status data (optional) status addr=second addr of sector stanby confirm locking change on q1, q0 (see sector locking state table for valid combinations.) start locking change complete write 60h (configuration setup) write 01h, d0h, or 2fh write 90h (read configuration) read sector lock status write ffh (read array) ye s no locking change confirmed ? 35 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 figure 11. protection register programming flowchart start write c0h (protection reg. program setup) full status check if desired read status register write protect. register address/data no ye s sr.7=1 ? program ccomplete read status register data(see above) full status check procedure program successful sr.3, sr.4= vpp range error 1,1 protection register programming error 0,1 attempted program to locked register aborted 1,1 sr.1, sr.4= sr.1, sr.4= bus command comments operation write protection data=c0h program setup write protection data=data to program program addr=location to program read status register data toggle ce# or oe# to update status register data standby check sr.7 1=wsm ready 0=wsm busy protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last operation to reset device to read array mode. bus command comments operation standby sr.1, sr.3, sr.4 0 1 1 vpp low standby 0 0 1 prot. reg. prog. error stanby 1 0 1 register locked: aborted sr.3 must be cleared, if set during a program at- tempt, before further attempts are allowed by the write state machine. sr.1,3,4 are only cleared by the clear status regis- ter command, in cases of multiple protection register program operations before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. 36 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 7 vpp program and erase voltage when vpp is between 1.65v and 3.6v, all program and erase current is drawn through the vcc pin. if vpp is driven by a logic signal, vih=1.65v. that is, vpp must remain above 1.65v to perform in-system flash update/ modifications. 7.1 vpp fast manufacturing programming when vpp is between 1.65v and 3.6v, all program and erase current is drawn through the vcc pin. if vpp is driven by a logic signal, vih=1.65v. that is, vpp must remain above 1.65v to perform in-system flash update/ modifications. when vpp is connected to a 12v power supply, the device draws program and erase current di- rectly from the vpp pin. 7.2 protection under vpp 38 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 table 9-3. cfi mode: device geometry data values description address h data h device size (2n bytes) 27 0017 flash device interface code (02=asynchronous x8/x16) 28 0001 29 0000 maximum number of bytes in multi-byte write (not supported) 2a 0000 2b 0000 number of erase block regions 2c 0002 erase block region 1 information t b [2e,2d] = # of blocks in region -1 2d 07 te [30, 2f] = size in multiples of 256-bytes 2e 00 00 2f 20 00 30 00 01 erase sector region 2 information 31 07 7e [32,31] = number of same-size sectors in region 2-1 32 00 00 [34,33] = region erase sector size in multiples of 256-bytes 33 20 00 34 00 01 table 9-4. cfi mode: primary vendor-specific extended query data values description a ddress h data h query-unique ascii string "pri" 35 0050 36 0052 37 0049 major version number, ascii 38 0031 minor version number, ascii 39 0030 optional feature & command support 3a 66 bit 0 chip erase supported (1=yes, 0=no) 3b 00 bit 1 suspend erase supported (1=yes, 0=no) 3c 00 bit 2 suspend program supported (1=yes, 0=no) 3d 00 bit 3 lock/unlock supported (1=yes, 0=no) bit 4 queued erase supported (1=yes, 0=no) bits 5-31 revered for future use; undefined bits are "0" sector lock status 3f 03 define which bits in the sector status register section of the query are 40 00 implemented. bit 0 sector lock status register lock/unlock bit (bit 0) active; (1=yes, 0=no) bit 1 sector lock status register lock/unlock bit (bit 1) active; (1=yes, 0=no) bits 2-15 reserved for future use. undefined bits are 0. vcc logic supply optimum program/erase voltage (highest performance) 41 33 bits 7-4 bcd value in volts bits 3-0 bcd value in 100mv vpp (programming) supply optimum program/erase voltage 42 c0 bits 7-4 hex value in volts bits 3-0 bcd value in 100mv 39 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 order information part no. access time operating standby package (ns) current max.(ma) current max.(ua) mx28f640c3bttc-90 90 30 5 48 pin tsop mx28f640c3bbtc-90 90 30 5 48 pin tsop MX28F640C3BTTC-12 120 30 5 48 pin tsop mx28f640c3bbtc-12 120 30 5 48 pin tsop mx28f640c3btti-90 90 30 5 48 pin tsop mx28f640c3bbti-90 90 30 5 48 pin tsop mx28f640c3btti-12 120 30 5 48 pin tsop mx28f640c3bbti-12 120 30 5 48 pin tsop 40 p/n:pm1084 mx28f640c3bt/b rev. 0.0, mar. 17, 2004 package information mx28f640c3bt/b m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. |
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